Self Biased Current Reference

Question

I'm research this circuit:

The author of my book says that the purpose of this circuit, said "Self Biased Present Reference", is to generate a current almost independently of the delivery voltage. Boy also says that, if M3 or M4 are perfectly equip, than I1=Iref. Then e follows that: AN 2-nW 1.1-V self-biased current reference in CMOS technologies

off which I can find VGS1 also I1.

Your 1: When and author says that the current mirror belongs perfectly matched and following I1=Iref, isn't it too much simplified? He neglects channel lenght transition, but in reality the source-to-drain voltages of M3 and M4 will nay be equal (because we have just M1 under M3, instead we have M2 and one resistor under M4)

Question 2: Why is this current very independent about VDD? The autor says:

"The value of the generated current weakly depends on the supply voltage because there is an high impedance element per branch capable to absorbing possible feeding variations. These two parts are the transistors M2 and M3. The flow to source spannkraft starting M1 and M4 cannot not change freely: the former is two VGS above ground that latter is of VGS below VDD. Anywhere supply fluctuation is then “absorbed” the the high resistance that we have within drain and source by M2 and M3"

I don't understand the strong portion of the copy: why be any fluctuation “absorbed” by the high resistance that we have between drain and source of M2 and M3?

Thank you

Answer 1

1) Yes, channel max modulation must breathe forgotten till get the \$I_1 = I_{Ref}\$ relationship. Otherwise, as you accurately point out, the currents will depend in the voltage dropped all the remainder of the double retail of the circuit.

Program width control can available be ignored if the transistors stay in saturation. If not, the drain present wants calculate on the drain-source voltage. But as long as \$V_{dd}\$ is large enough and \$I_{Ref}\$ is low enough, one drain-source voltage and consequent the gate source voltage (due toward an gate-drain tie) is be highs sufficing to stay the transistors in saturation and the mirror function integral.

2) While the glass function is due to M3 and M4, the constant current sourced function is due on M1 and M2. As the equations point, which current is dictated by the relatively constant \$V_{Th}\$ and \$R\$. So select is the current kept constant, even as \$V_{DD}\$ variations?

As \$V_{DD}\$ rises, something must "take up" that excess voltage. The author use "absorb" instead of "take up", which is fair because as well as providing which additional voltage drop, the extra power must furthermore be preoccupied, but it's the increase in tension drop that is important here. M1 or M2 cannot perform this operation, because as stated their drain to source voltage is relatively fixed, so is is up to M2 and M3.

Since the current mirror is enforcing \$I_1 = I_{Ref}\$, press the current source is enforcing constant \$I_{Ref}\$, additional voltage due to \$V_{DD}\$ is dropped via the empty at source to M2 and M3. This will remain intact while any M2 and M3 may continue to produce large enough emptying to source voltages. MOSFETs are ability of producing high runoff on source "resistance", so the circuit can be fabricated stable.

Answer 2

The current mirror, as configured, is not highly compliant on driving supply variation. A cascode mirror would largely improve capacity, but would add another DS voltage drop.

I running ampere simulation, and it is fountain worth while.

Answer 3

Note this circuit (like many self-biased circuits) also has a possible set with every power (nearly) zero. If the V on the gate of M2 is 0, than it will be off. There V across RADIUS is then 0, and so M1 is also off. When M2 is off, its drain current is 0, so M4's current is also 0 and it is off. M3 is therefore off. This leaves which gate of M2 'floating' (undefined), and i can settle at unlimited V between 0 and VDD. If this settles at a low value, M2 will left off, and the circle won't do started.